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CXP854P60
CMOS 8-bit Single-chip Microcomputer
Description The CXP854P60 are a highly integrated microcomputers composed of a 8-bit CPU, PROM, RAM, and I/O ports. These chips feature many other highperformance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time-base timer, vector interrupt, onscreen display function, I2C bus interface, PWM generator, remote control receiver, HSYNC counter, and watchdog timer. Also, the CXP854P60 provides power-on reset and sleep functions. The designers have ensured low power consumption for these powerful microcomputers. Incorporating a one-time PROM, the CXP854P60 has an equivalent function to the CXP85460 and character ROM for OSD can be written. Therefore, it is suitable for evaluation in system development and for the production of small amounts. 64 pin SDIP (PIastic) 64 pin QFP (PIastic)
Structure Silicon gate CMOS IC
Features * Instruction set which supports a wide array of data types-213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and boolean operations. * Minimum instruction cycle 0.5s/8MHz * On-chip PROM 60K bytes (For program) 10K bytes (For OSD) * On-chip RAM 960 bytes * On-screen display function 12 x 18 dots, 384 types, 12lines of 32 characters Black frame output, half blanking, shadow, background color on full screen Double scanning mode supported includes jitter elimination circuit 2C bus interface *I * 14-bit PWM output, 8-bit PWM output (8 channels) * Remote control receiver circuit * 8-bit A/D converter (4 channels, 20s conversion time/4MHz, 8MHz) * HSYNC counter (2channels) * Watchdog timer * 8-bit synchronized serial I/O * 8-bit timer, 8-bit timer/counter, 19-bit time-base timer * General purpose input/output 32-line I/O (bit-selectable input/output), also 6-line input, 10-line output (internal 8-line Nch-O/D) * Interrupts 13 factors, 13 vectors, multiple interrupt possible * Standby mode SLEEP * Package 64-pin plastic SDIP/QFP
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E95109-ST
Block Diagram
MP VDD VSS
PE0/INT0
PE1/INT1
PD0/INT2
EXTAL
XTAL
RST
Vpp
XLC EXLC R G B I YS YM PA7/HSYNC PA6/VSYNC 2
ON SCREEN DISPLAY
PORT A
SPC700 CPU CORE
CLOCK GEN./ SYSTEM CONTROL
PA0 to PA7
INTERRUPT CONTROLLER
PD3/SI PD2/SO PD1/SCK PROM 60K RAM 960 BYTES
SERIAL I/O
PD4/HS0 WATCH DOG TIMER
HSYNC COUNTER 0 PRESCALER/ TIME BASE TIMER PE0 to PE5 PE6 to PE7
PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 14BIT PWM
I2C INTERFACE UNIT
8 BIT PWM 8CH
PE6/PWM
PF0/PWM0 to PF7/PWM7
PORT F
PE2/AN0 to PE5/AN3
A/D CONVERTER
PORT E
PD5/HS1
HSYNC COUNTER 1
PORT D
-2-
FIFO
PD6/RMC
REMOCON
PORT C
PD7/EC PE7/TO
TIMER/COUNTER
PORT B
2
PB0 to PB7
PC0 to PC7
PD0 to PD7
PF0 to PF7
CXP854P60
CXP854P60
Pin Assignment (Top View)
HSYNC/PA7 VSYNC/PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 EC/PD7 RMC/PD6 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD Vpp VSS MP PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 YM YS I B G R EXLC XLC PE0/INT0 PE1/INT1 PE2/AN0 PE3/AN1 PE4/AN2 PE5/AN3 PE6/PWM PE7/TO RST EXTAL XTAL PD0/INT2
PA7/HSYNC
PA6/VSYNC
PF0/PWM0
PF1/PWM1
PF2/PWM2
Note) 1. Vpp pin 63 must be connected to VDD. 2. Vss pins 32 and 62 must have a common GND. 3. MP pin 61 must be connected to GND.
PA3
PA2
PA4
PA5
Vpp
VSS
VDD
64
63
62
61
60
59
58
57
MP
56
55
54 53
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 EC/PD7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PF3/PWM3 PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 YM YS I B G R EXLC XLC PE0/INT0 PE1/INT1 PE2/AN0 PE3/AN1 PE4/AN2 PE5/AN3
TO/PE7
XTAL
RMC/PD6
Note) 1. Vpp pin 56 must be connected to VDD. 2. Vss pins 26 and 58 must have a common GND. 3. MP pin 55 must be connected to GND.
PWM/PE6
SCK/PD1
SO/PD2
INT2/PD0
HS1/PD5
HS0/PD4
SI/PD3
EXTAL
RST
VSS
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CXP854P60
Pin Functions Pin Name PA0 to PA5 PA6/VSYNC PA7/HSYNC PB0 to PB7 I/O I/O/Input I/O/Input I/O I/O Function (Port A) Single bit selectable 8-bit port. (8 lines) CRT display vertical synchronization signal input pin. CRT display horizontal synchronization signal input pin. (Port B) Single bit selectable 8-bit port. (8 lines) (Port C) Single bit selectable 8-bit port. (8 lines) Input pin for external interrupt request. Active on falling edge. Serial clock pin. (Port D) Single bit selectable Serial data output pin. 8-bit port. Serial data input pin. 12mA sink current drive possible. HSYNC counter (CH0) input pin. (8 lines) HSYNC counter (CH1) input pin. Remote control receiver circuit input pin. External event timer/counter input pin. Input pin for external interrupt request. Active falling edge. (2 lines) Analog input pin for A/D converter. (4 lines) 14-bit PWM output pin. (CMOS output) Square wave output for timer 1. (50% duty cycle) (Port F) 8-bit output port with large current (12mA) N-ch open drain output. Lower 4 bits middle voltage tolerance (12V), upper 4 bits 5V suppression. (8 lines) 8-bit PWM output pin. (8-lines)
PC0 to PC7
I/O
PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC PE0/INT0 PE1/INT1 PE2/AN0 to PE5/AN3 PE6/PWM PE7/TO PF0/PWM0 to PF3/PWM3 PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 R, G, B, I, YS, YM
I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input Input/Input (Port E) 8-bit port, lower 6 bits for input, upper 2 bits for output. (8 lines)
Input/Input
Output/Output Output/Output
Output/Output
Output/Output/ I/O
I2C bus interface transfer clock I/O pin.
Output/Output/ I/O Output
I2C bus interface transfer data I/O pin.
CRT display 6-bit output pin.
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CXP854P60
Pin Name EXLC XLC EXTAL XTAL RST MP Vpp VDD Vss Input
I/O
Function CRT display clock oscillator I/O pin. Oscillator frequency is determined external L, C circuit. System clock oscillator crystal connection pin. When using an external clock, input to EXTAL pin and leave XTAL pin open. "L" level active system reset. This pin also acts as an I/O pin during power up. While internal power-on reset function is talking place a "L" level is output. Test mode input pin. Must be connected to GND. Positive power supply pin for incorporated PROM writing. Under normal operating conditions, connect to VDD. Positive supply voltage pin. GND. Both Vss pins should be connected to common GND.
Output Input Output I/O Input
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CXP854P60
Pin Equivalent I/O Circuit Pin Port A Port B Port C PA0 to PA5 PB0 to PB7 PC0 to PC7
Port A data Port B data Port C data Port A direction Port B direction Port C direction IP Data bus RD (Port A, B, C) Input protection circuit
Circuit format
When reset
Hi-Z
22 lines Port A
Port A data Port A direction
PA6/VSYNC PA7/HSYNC
Data bus RD (Port A) VSYNC HSYNC Schmitt input Input multiplexer
IP
Input protection circuit
Hi-Z
2 lines Port D PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC
Data bus RD (Port D) INT2, SI, HS0, HS1, RMC, EC Schmitt input IP
Port D data Port D direction Large current source 12mA
Hi-Z
6 lines
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CXP854P60
Pin Port D
Circuit format
When reset
SCK or SO Output enable
PD1/SCK PD2/SO
Large current source 12mA Port D data Port D direction Schmitt input RD (Port D) SCK only IP
Hi-Z
Data bus
2 lines Port E PE0/INT0 PE1/INT1 2 lines Port E
Input multiplexer Schmitt input IP (To interrupt circuit)
Hi-Z
Data bus RD (Port E)
PE2/AN0 to PE5/AN3
IP
To A/D converter
Hi-Z
Data bus
4 lines Port E
TO, PWM
RD (Port E)
PE6/PWM PE7/TO
Port E data Port E selection
H level
2 lines
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CXP854P60
Pin Port F PF0/PWM0 to PF3/PWM3
PWM
Circuit format
When reset
12V voltage torelance Port F data Port F selection Large current source 12mA
Hi-Z
4 lines Port F
SCL, SDA
PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1
I2C output enable PWM
Large current source 12mA
Hi-Z
Port F data Port F selection Schmitt input SCL, SDA (To I2C circuit) BUS SW To other I2C pins IP
4 lines
R G B I YS YM 6 lines
R, G, B, I, YS, YM
Output polarity To output polarity register Writing data to port register brings output from high impedance to active
Hi-Z
EXLC XLC
EXLC
IP
Oscillator control
Oscillation halted
XLC IP CRT display clock
2 lines
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CXP854P60
Pin
Circuit format
When reset
EXTAL XTAL
* Diagram indicates equivalent circuit during oscillation EXTAL IP * Feedback resistor is disconnected during STOP
Oscillation
XTAL
2 lines
Pull-up resistor
RST
Schmitt input
L level
From power-on reset circuit
1 line
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CXP854P60
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Medium voltage tolerance output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation Symbol VDD Vpp VIN VOUT VOUTP IOH IOH IOL IOLC IOL Topr Tstg PD Ratings -0.3 to +7.0 -0.3 to +13.0 -0.3 to +7.01 -0.3 to +7.01 -0.3 to +15.0 -5 -50 15 20 130 -10 to +75 -55 to +150 1000 600 Unit V V V V V mA mA mA mA mA C C mW mW SDIP QFP Pins PF0 to PF3
(Vss = 0V) Remarks
Incorporated PROM
Total of all output pins Excludes large current output Large current output2 Total of all output pins
1 VIN and VOUT should not exceed VDD + 0.3V. 2 The large current driver for the PD and PF ports is a N-ch transistor. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
Recommended Operating Conditions Item Symbol VDD Supply voltage Vpp VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr Min. 4.5 3.5 2.5 Max. 5.5 5.5 5.5 Unit V V V V V V V V V V C Remarks Safe operating range
(Vss =0V)
Safe operating range for low speed data1 Safe operating range for data retention during STOP 5 I2C Schmitt input included2 CMOS Schmitt input3 EXTAL pin4 I2C Schmitt input included2 CMOS Schmitt input3 EXTAL pin4
Vpp = VDD 0.7VDD 0.8VDD VDD - 0.4 0 0 -0.3 -10 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75
1 Rating for 1/16 frequency mode and sleep mode. 2 Normal input port (All pins PA, PB, PC, PE2 to PE5), PF4 to PF7 pins. 3 Includes PD0/INT2, PD1/SCK, PD2, PD3/SI, PD4/HS0, PD5/HS1, PD6/RMC, PD7/EC, PE0/INT0, PE1/INT1, HSYNC, VSYNC, RST pins. 4 Rating applies to external clock input only. 5 Vpp and VDD should be set to a same voltage. - 10 -
CXP854P60
DC Characteristics Item High level output voltage
Symbol
(Ta = -10 to +75C, Vss = 0V) Pin Condition Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 0.5 -0.5 -1.5 40 -40 -400 10 50 10 120 Typ. Max. Unit V V V V V V V A A A A A A
VOH
PA to PD, PE6, PE7, VDD = 4.5V, IOH = -0.5mA R, G, B, I, YS, YM VDD = 4.5V, IOH = -1.2mA PA to PD, PE6, PE7, VDD = 4.5V, IOL = 1.8mA R, G, B, I, YS, YM, VDD = 4.5V, IOL = 3.6mA PF0 to PF3, RST
Low level output voltage
VOL
PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1)
VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V
IIHE Input current IIHL IILR I/O leakage current Open drain output leak current (N-ch Tr off case) I2C bus switch connection impedance (Output Tr off case) IIZ
EXTAL RST PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM PF0 to PF3
VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V Operating mode (1/2, clock rate) 8MHz crystal oscillator (C1 = C2 = 22pF) All output pins open SLEEP mode STOP mode2
ILOH PF4 to PF7 RBS SCL0: SCL1 SDA0: SDA1
IDD Supply current IDDSL IDDST Input capacitance CIN Pins other than VDD and Vss VDD1
20
35
mA
1.0 -- -- 10
3 -- 20
mA A pF
1MHz clock 0V for non-measurement pins
1 Rating applies only if OSD oscillator is halted. 2 This device does not enter in the stop mode.
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CXP854P60
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock rise and fall times Event counter input clock pulse widtth Event counter input clock rise and fall times System fC Pin XTAL EXTAL EXTAL EXTAL EC EC
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig 1, Fig 2 External clock drive Fig. 3 Fig. 3 Min. 3.5 Max. 9 Unit MHz ns ns ns 20 ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
50 200
tsys + 50
tsys indicates one of three values according to the contents of the clock control register. (For CPU clock
selection.) tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
Crystal oscillator Ceramic oscillator
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
OPEN
Fig. 3. Event count clock timing
0.8VDD EC 0.2VDD
tEH
tEF
tEL
tER
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CXP854P60
(2) Serial transfer Item SCK cycle time SCK high and low level widths SI input set-up time (referenced to SCK ) SI input hold time (referenced to SCK ) SCK SO delay time System Pin SCK Condition Input mode Output mode SCK
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Min. 1000 8000/fc 400 4000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
SCK input mode SCK output mode
SI
SCK input mode SCK output mode
SI
SCK input mode SCK output mode
SO
SCK input mode SCK output mode
Note) For SCK output mode, in addition to output delay time SO capacitance must be 50pF + 1TTL.
Fig. 4. Serial transfer timing
tKCY tKL tKH
0.8VDD SCK 0.2VDD
tSIK
tKSI
0.8VDD SI Input data 0.2VDD
tKSO
0.8VDD SO 0.2VDD Output data
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CXP854P60
(3) Interrupt, Reset input Item External interrupt high and low level widths Reset input low level width
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin INT0 to INT2 RST Condition Min. 1 8/fc Max. Unit s s
tIH tIL tRSL
Fig. 5. Interrupt input timing
tIH tIL
INT0 to INT2 (falling edge)
0.8VDD 0.2VDD
Fig. 6. RST input timing
tRSL
RST 0.2VDD
(4) Power-on reset Power on reset Item Power supply rise time Power supply cutt-off time Symbol Pin VDD
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Power-on reset Repeated power-on reset Min. 0.05 1 Max. 50 Unit ms ms
tR tOFF
Fig. 7. Power-on reset
4.5V VDD 0.2V tR Take care when turning on power. tOFF 0.2V
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CXP854P60
(5) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Ta = 25C VDD = 5.0V Vss = 0V Symbol Pin Condition
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Min. Typ. Max. 8 1 -10 4910 160/fADC3 12/fADC3 AN0 to AN3 0 VDD 10 4970 70 5030 Unit Bits LSB mV mV s s V
tCONV tSAMP
VIAN
Fig. 8. Definitions for A/D converter terms
FFH FEH
Digital conversion value
Linearity error
1 VZT: Digital conversion values change between 00H 01H. 2 VFT: Digital conversion values change between 0EH 0FH. 3 fADC indicates the below values due to the bit6 (CKS) of A/D control registor (address: 00F6H) and the Bit 7 (PCK1) and Bit 6 (PCK0) of clock control registor (address: 00FEH) CKS 0 (/2 selection) 1 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 fADC = fC fADC = fC/2 fADC = fC/8
01H 00H
VZT Analog input
VFT
PCK1, 0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16)
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CXP854P60
(6) I2C bus timing Item SCL clock frequency Bus free time before starting transfer Hold time for starting transfer Clock low level width Clock high level width Set-up time for repeated transfers Data hold time Data set-up time SDA, SCL rise time SDA, SCL fall time Set-up time for transfer completion Symbol fSLC
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Pin SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Condition Min. 0 4.7 4.0 4.7 4.0 4.7 0 0.25 1 0.3 Max. 100 Unit kHz s s s s s s s s s s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
Since SCL rise time (max: 300ns) is not considered part of data hold time, allow at least 300ns.
Fig. 9. I2C bus transfer data timing
SDA tBUF tR tF tHD; STA
SCL tHD; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STA tSU; STO P
Fig. 10. I2C device suggested circuit
I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS
I2C device RS RP RP
* A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1). * The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300 or less) can be used to reduce spike noise caused by CRT flashover.
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CXP854P60
(7) OSD (On Screen Display) timing Item Symbol Pin EXLC XLC HSYNC HSYNC VSYNC Condiiton
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Shadow Existent Min. 4 1.2 200 1.0 Max. 71 142 Shadow Non-existent Min. 4 1.2 200 1.0 Max. 111 162 Unit
OSD clock frequency HSYNC pulse width HSYNC afterwrite rise and fall times VSYNC afterwrite rise and fall times
fOSC
Fig. 12 Fig. 11 Fig. 11 Fig. 11
MHz s ns s
tHWD tHCG tVCG
1 Oscillator clock at 4MHz operation 2 Oscillator clock at 8MHz operation
Fig. 11. OSD timing
tHWD tHCG
HSYNC For OPOL register (01FAH) bit 7 at "0"
0.8VDD
0.2VDD
tVCG
VSYNC For OPOL register (01FAH) bit 6 at "0"
0.8VDD
0.2VDD
Fig. 12. LC oscillator circuit connection
EXLC
XLC
L
C1
C2
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CXP854P60
Supplement Fig. 13. SPC700 Series recommended oscillation circuit (i) (ii)
EXTAL
XTAL Rd
EXTAL
XTAL Rd
C1
C2 C1 C2
Manufacturer
Model CSA4.00MG CSA4.19MG
fc (MHz) 4.00 4.19 8.00 4.00 4.19 8.00 4.00
C1 (pF)
C2 (pF)
Rd ()
Circuit Example
(i) 30 30 0 (ii)
MURATA MFG CO., LTD.
CSA8.00MTZ CST4.00MGW CST4.19MGW CST8.00MTW
RIVER ELETEC CO., LTD.
HC-49/U03
4.19 8.00 4.00
12
12
0
(i)
KINSEKI LTD.
HC-49/U(-S)
4.19 8.00
27
27
0
(i)
Indicates types with on-chip grounding capacitors (C1 and C2).
Product List Option item Package Program ROM capacitance Reset pin pull-up resistor Power-on reset circuit Font data Mask product 64-pin plastic SDIP/QFP 52K/60K byte Existent/Non-existent Existent/Non-existent User specified CXP854P60S-1CXP854P60Q-164-pin plastic SDIP/QFP PROM 60K byte Existent Existent User specified (PROM)
The font data for the one-time PROM version is operated in the same way as the program writing.
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CXP854P60
Fig. 14. Characteristics curves
IDD vs. VDD
(fc = 8MHz, Ta = 25C, Typical) 20 1/2 frequency mode 1/4 frequency mode 18 10 16
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
1/2 frequency mode
IDD - Supply current [mA]
1/16 frequency mode 14
IDD - Supply current [mA]
SLEEP mode 1
12
10 1/4 frequency mode 8
6 0.1 2 3 4 5 6 4 1/16 frequency mode 2 SLEEP mode 0 1 5 fc - System clock [MHz] 10
VDD - Supply voltage [V]
Parameter Curve for OSD Oscillator L vs. C
(Analytically calculated value) 100
5.0MHz
L - Inductance [H]
6.5MHz 10
13.0MHz fOSC = 0 50 C1, C2 - Capacitance [pF] 100 1 2 LC C = C1 // C2
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CXP854P60
Package Outline
Unit: mm
64PIN SDIP (PLASTIC) 750mil
+ 0.4 57.6 - 0.1 64 33
19.05 + 0.3 17.1 - 0.1
+ 0.1 0.05 0.25 -
0 to 15 32 0.5 0.1 0.9 0.15
1 1.778
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 8.6g
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
3 MIN
0.5 MIN + 0.4 4.75 - 0.1
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
19 + 0.35 2.75 - 0.15 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER /42 ALLOY 1.5g
- 20 -
0.8 0.2
16.3

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